Static random access memory cells

ABSTRACT

A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second invertor including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first invertor being cross-coupled with the second invertor, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first invertor; a second access transistor having an active terminal connected to the second invertor; and an isolator isolating the first pullup transistor from the second pullup transistor.

TECHNICAL FIELD

[0001] The invention relates to non-volatile static memory devices. Moreparticularly, the invention relates to methods of manufacturing staticrandom access memory devices.

BACKGROUND OF THE INVENTION

[0002] One known type of static read/write memory cell is a high-densitystatic random access memory (SRAM). A static memory cell ischaracterized by operation in one of two mutually-exclusive andself-maintaining operating states. Each operating state defines one ofthe two possible binary bit values, zero or one. A static memory celltypically has an output which reflects the operating state of the memorycell. Such an output produces a “high” voltage to indicate a “set”operating state. The memory cell output produces a“low” voltage toindicate a “reset” operating state. A low or reset output voltageusually represents a binary value of zero, while a high or set outputvoltage represents a binary value of one.

[0003] A static memory cell is said to be bistable because it has twostable or self-maintaining operating states, corresponding to twodifferent output voltages. Without external stimuli, a static memorycell will operate continuously in a single one of its two operatingstates. It has internal feedback to maintain a stable output voltage,corresponding to the operating state of the memory cell, as long as thememory cell receives power.

[0004] The two possible output voltages produced by a static memory cellcorrespond generally to upper (V_(cc)internal-V_(T)) and lower (V_(ss))circuit supply voltages. Intermediate output voltages, between the upper(V_(cc)V_(T)) and lower (V_(SS)) circuit supply voltages, generally donot occur except for during brief periods of memory cell power-up andduring transitions from one operating state to the other operatingstate.

[0005] The operation of a static memory cell is in contrast to othertypes of memory cells such as dynamic cells which do not have stableoperating states. A dynamic memory cell can be programmed to store avoltage which represents one of two binary values, but requires periodicreprogramming or “refreshing” to maintain this voltage for more thanvery short time periods.

[0006] A dynamic memory cell has no internal feedback to maintain astable output voltage. Without refreshing, the output of a dynamicmemory cell will drift toward intermediate or indeterminate voltages,resulting in loss of data. Dynamic memory cells are used in spite ofthis limitation because of the significantly greater packaging densitieswhich can be attained. For instance, a dynamic memory cell can befabricated with a single MOSFET transistor, rather than the sixtransistors typically required in a static memory cell. Because of thesignificantly different architectural arrangements and functionalrequirements of static and dynamic memory cells and circuits, staticmemory design has developed along generally different paths than has thedesign of dynamic memories.

[0007] A static memory cell 10 is illustrated in FIG. 1. Static memorycell 10 generally comprises first and second inverters 12 and 14 whichare cross-coupled to form a bistable flip-flop. Inverters 12 and 14 areformed by first and second n-channel pulldown (driver) transistors N1and N2, and first and second pchannel load (pullup) transistors P1 andP2. Transistors N1 and N2 are typically metal oxide silicon field effecttransistors (MOSFETs) formed in an underlying silicon semiconductorsubstrate. P-channel transistors P1 and P2 can be thin film transistorsformed above the driver transistors or bulk devices.

[0008] Driver transistors N1 and N2 have respective source regions 66and 68 tied to a low reference or circuit supply voltage, labelledV_(ss), and typically referred to as “ground.” Driver transistors N1 andN2 have respective drain regions 64 and 62, and respective gates. Loadtransistors P1 and P2 have respective source regions 78 and 80 tied to ahigh reference or circuit supply voltage, labelled V_(cc), and haverespective drain regions 70 and 72 tied to the drains 64 and 62,respectively, of the corresponding driver transistors N1 and N2. Thegate of load transistor P1 is connected to the gate of driver transistorN1. The gate to load transistor P2 is connected to the gate of thedriver transistor N2.

[0009] Inverter 12 has an inverter output 20 formed by the drain ofdriver transistor N1. Similarly, inverter 14 has an inverter output 22formed by the drain of driver transistor N2. Inverter 12 has an inverterinput 76 formed by the gate of driver transistor N1. Inverter 14 has aninverter input 74 formed by the gate of driver transistor N2.

[0010] The inputs and outputs of inverters 12 and 14 are cross-coupledto form a flip-flop having a pair of complementary two-state outputs.Specifically, inverter output 20 is coupled to inverter input 74 vialine 26, and inverter output 22 is coupled to inverter input 76 via line24. In this configuration, inverter outputs 20 and 22 form thecomplementary two-state outputs of the flip-flop.

[0011] A memory flip-flop such as that described typically forms onememory element of an integrated array of static memory elements. Aplurality of access transistors, such as access transistors 30 and 32,are used to selectively address and access individual memory elementswithin the array. Access transistor 30 has one active terminal 58connected to cross-coupled inverter output 20. Access transistor 32 hasone active terminal 60 connected to cross-coupled inverter output 22. Apair of complementary column or bit lines 34 and 36 shown, are connectedto the remaining active terminals 56 and 54 of access transistors 30 and32, respectively. A row or word line 38 is connected to the gates ofaccess transistors 30 and 32. In the illustrated embodiment, accesstransistors 30 and 32 are n-channel transistors.

[0012] Reading static memory cell 10 requires activating row line 38 toconnect inverter outputs 20 and 22 to column lines 34 and 36. Writing tostatic memory cell 10 requires complementary logic voltage on columnlines 34 and 36 with row line 38 activated. This forces the outputs tothe selected logic voltages, which will be maintained as long as poweris supplied to the memory cell, or until the memory cell isreprogrammed.

[0013] In semiconductor processing, there is a continuing desire to makecircuits denser, and to place components closer and closer together toreduce the size of circuits. However, certain processing steps employedin manufacturing static memory cells such as the static memory cellshown in FIG. 1 result in some undesirable variations between desiredresults and actual results in the manufacturing process. For example,there are precision limits inherent in photolithography. Another processthat results in some undesirable variations between desired results andactual results is called LOCOS isolation (for LOCal Oxidation ofSilicon). LOCOS isolation is a common technique for isolating devices.

[0014] Implementing a static memory cell on an integrated circuitinvolves connecting isolated circuit components or devices, such asinverters and access transistors, through specific electrical paths.When fabricating integrated circuits into a semiconductor substrate,devices within the substrate must be electrically isolated from otherdevices within the substrate. The devices are subsequentlyinterconnected to create specific desired circuit configurations.

[0015] LOCOS isolation involves the formation of a semi-recessed oxidein the non-active (or field) areas of the bulk substrate. Such oxide istypically thermally grown by means of wet oxidation of the bulk siliconsubstrate at temperatures of around 1000° C. for two to six hours. Theoxide grows where there is no masking material over other silicon areason the substrate. A typical masking material used to cover areas wherefield oxide is not desired is nitride, such as Si₃N₄.

[0016] However, at the edges of a nitride mask, some of the oxidant alsodiffuses laterally immediately therebeneath. This causes oxide to growunder and lift the nitride edges. The shape of the oxide at the nitrideedges is that of a slowly tapering oxide wedge that merges into apreviously formed thin layer of pad oxide, and has been termed as a“birds beak”. The bird's beak is generally a lateral extension of thefield oxide into the active areas of devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0018]FIG. 1 is a circuit schematic of a static random access memorycell.

[0019]FIG. 2 is a broken away portion of circuit layout diagramillustrating a novel layout for manufacturing a plurality of staticrandom access memory cells including cells such as the cell shown inFIG. 1.

[0020]FIG. 3 illustrates the same layout shown in FIG. 2, except withinformation removed for increased clarity. For example, localinterconnects that are shown in FIG. 2 are deleted in FIG. 3.

[0021]FIG. 4 illustrates pullback that results during manufacturing whenusing the layout shown in FIGS. 2 and 3.

[0022]FIG. 5 is a circuit schematic of an improved static memory cellembodying another novel layout.

[0023]FIG. 6 is a broken away portion of a circuit layout diagramillustrating a method of manufacturing a plurality of static randomaccess memory cells including cells such as the cell shown in FIG. 5.

[0024]FIG. 7 is a circuit layout diagram for the layout shown in FIG. 6,with information removed for increased clarity. For example, localinterconnects that are shown in FIG. 6 are deleted.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] The invention provides a static random access memory cellcomprising a first p-channel pullup transistor having a gate, drain, andsource; a first nchannel pulldown transistor having a gate, drain, andsource; a second p-channel pullup transistor having a gate, drain, andsource; a second n-channel pulldown transistor having a gate, drain, andsource; the source of the first pullup transistor being adapted to beconnected to a first voltage; the source of the second pullup transistorbeing adapted to be connected to the first voltage; the drain of thefirst pulldown transistor being connected to the drain of the firstpullup transistor; the drain of the second pulldown transistor beingconnected to the drain of the second pullup transistor; the source ofthe first pulldown transistor being adapted to be connected to a secondvoltage lower than the first voltage; the source of the second pulldowntransistor being adapted to be connected to the second voltage; the gateof the first pullup transistor being connected to the gate of the firstpulldown transistor; the gate of the second pullup transistor beingconnected to the gate of the second pulldown transistor; the firstpullup transistor and the first pulldown transistor together defining afirst invertor having an output defined by the drain of the firstpulldown transistor and an input defined by the gate of the firstpulldown transistor, the second pullup transistor and the secondpulldown transistor together defining a second invertor having an outputdefined by the drain of the second pulldown transistor and an inputdefined by the gate of the second pulldown transistor, the input of thefirst invertor being connected to the output of the second inverter, andthe input of the second invertor being connected to the output of thefirst invertor; and a p-channel isolation transistor connected betweenthe drain of the first pullup transistor and the drain of the secondpullup transistor, and having a gate.

[0026] In one aspect of the invention, a static random access memorycell comprises a first invertor) including a first p-channel pulluptransistor, and a first n-channel pulldown transistor in series with thefirst p-channel pullup transistor; a second invertor including a secondp-channel pullup transistor, and a second n-channel pulldown transistorin series with the second a-channel pullup transistor, the firstinvertor being cross-coupled with the second invertor, the first andsecond pullup transistors sharing a common active area; a first accesstransistor having an active terminal connected to the first invertor; asecond access transistor having an active terminal connected to thesecond invertor; and an isolator isolating the first pullup transistorfrom the second pullup transistor.

[0027] In one aspect of the invention, a method of manufacturing astatic random access memory cell including first and secondcross-coupled invertors, each invertor including a pchannel transistorconnected in series with an n-channel transistor, the p-channeltransistors having sources that are connected to each other and that areadapted to be connected to a common first voltage, and the pchanneltransistors having respective drains; the n-channel transistors havingrespective sources that are connected to each other and that are adaptedto be connected to a common second voltage, lower than the firstvoltage, and the n-channel transistors having respective drains; themethod comprising the following steps: providing a silicon substrate;defining the first and second inverters relative to the substrate andincluding an active area common to drains of the p-channel transistors;and defining an isolation gate relative to the common active area,between the drains of the p-channel transistors

[0028] In one aspect of the invention, a method of manufacturing a waferincluding a plurality of static random access memory cells, each cellincluding first and second cross-coupled invertors, each invertorincluding a p-channel transistor connected in series with an n-channeltransistor, the p-channel transistors having sources that are connectedtogether and that are adapted to be connected, to a common firstvoltage, and having respective drains; the n-channel transistors havingsources that are connected together and that are adapted to be connectedto a common second voltage, lower than the first voltage, and havingrespective drains; the method comprising the following steps: providinga silicon substrate; defining active areas relative to the substrate forthe static random access memory cells, the active areas including anactive area having the general shape of a stepladder, including twoparallel, spaced apart sides, and a plurality of parallel, spaced apartportions extending between the sides, such that the sides define drainsof a plurality of the p-channel transistors; and defining respectiveisolation gates relative to active areas, between the drains of thep-channel transistors within each static random access memory cell.

[0029]FIG. 2 illustrates a circuit layout diagram illustrating a novellayout for manufacturing a plurality of static random access memorycells including cells such as the cell shown in FIG. 1. Circuits such asthe one shown in FIG. 1 are manufactured using silicon processingtechniques which are known in the art. There are many different ways oflaying out any circuit on a bulk substrate.

[0030] In the layout of FIG. 2, active areas of the bulk substrate(e.g., the silicon wafer itself or doped areas beneath the wafersurface) are designated by reference numeral 42, polysilicon isdesignated by reference numeral 44, local interconnects (straps formedof a conductor such as Titanium Nitride) are designated by referencenumeral 48, exhumed contacts are designated by reference numeral 46, Vccmetal is designated by reference numeral 50, and Vss metal is designatedby reference numeral 52. The term “exhumed contact” refers to contactswhich connect polysilicon to a local interconnect. This is in contrastto a buried contact.

[0031] Generally speaking, transistors are formed where polysllicon 44intersects an active area 42. There is generally no physical distinctionbetween the source and drain of any of the transistors shown; instead,the distinction is based on the direction of current flow when thestatic memory cell is connected to a power source.

[0032] In the embodiment shown in FIG. 2, of the areas shown, the orderin which they are formed is as follows: active areas, then polysilicon,then local interconnects, and then exhumed contacts.

[0033] Reference numerals are provided on FIG. 2 which correspond withreference numerals shown in FIG. 1 to illustrate how the circuit of FIG.1 is laid out in one embodiment. For example, the source of transistorP1 is indicated by reference numeral 78 in both FIGS. 1 and 2; the drainof transistor P1 is indicated by reference numeral 70; the source oftransistor P2 is indicated by reference numeral 80; the drain oftransistor P2 is indicated by reference numeral 72; the source oftransistor N1 is indicated by reference numeral 66; the drain oftransistor N1 is indicated by reference numeral 64; the source oftransistor N2 is indicated by reference numeral 68; and the drain oftransistor N2 is indicated by reference numeral 62 in both FIGS. 1 and2. Remaining white regions in these layout views (FIGS. 2-3, and 6-7)represent field oxide.

[0034]FIG. 3 illustrates the same layout shown in FIG. 2, except at anearlier processing step for increased clarity. For example, localinterconnects, Vcc metal, and Vss metal shown in FIG. 2 are not includedin FIG. 3.

[0035] As best seen in FIG. 3, the active areas 42 include areas in thegeneral shape of a letter “H” (rotated 90°), as well as areas in thegeneral shape of a dog bone (rotated 90°). The dog bone shaped areas arewhere the n-channel transistors N1 and N2 are formed, and the H-shapedregions are where the p-channel transistors P1 and P2 are formed.Accordingly, for an intrinsic p-type monocrystalline substrate, anelongated n-well is provided centrally; e.g., where the center of theH-shaped regions intersect with Vcc metal. Each SRAM cell is containedrelative to two opposed legs of separate H's and two corners of separatebut adjacent dogbones which are adjacent to those legs of the H's.

[0036] There is a problem relating to the spacing of the ends of H'srelative to adjacent H's. During the manufacturing process, there issignificant pullback of the H-shaped active areas that form the drains70 and 72 of the pullup transistors P1 and P2. This is illustrated inFIG. 4, which represents two adjacent H-shaped active area regions 42intersecting polysilicon 44. The adjacent H-shaped active area regions42 are separated by field oxide in the layout shown in FIGS. 2 and 3.

[0037] The desired shape of the H-shaped regions 42 is indicated in FIG.4 by outer dashed line 88. This is the shape of the active area as drawnon a reticle employed in defining the H-shaped regions 42. Inner dashedline 90 represents the shape of the area after photolithography (I-line365 nm). Finally, the shape after aggressive LOCOS isolation (describedabove in the Background of the Invention) is illustrated with solid line92. Encroachment takes place along two dimensions; i.e., along both thelength and the width of the “H”. The most extreme pullback occurs at theends of the legs of the “H” where the drains 70 and 72 of the p-channeltransistors P1 and P2 are defined. Also, the polysilicon has anassociated spacer (e.g., 800 angstroms wide) which reduces the size ofthe active area eve further.

[0038] Because of these pullback effects, the lengths of the legs of theH-shaped regions must be exaggerated so that contact can be made betweenthe drains of the p-channel transistors P1 and P2.

[0039] The transistors P1 and P2 are defined where polysilicon 44traverses the active area 42. Active areas 42 which are not traversed bypolysilicon 44 are doped to form the source and drain regions of thetransistors. The drains 70 and 72 of the p-channel transistors need tobe contacted with local interconnect 48 in the layout shown in FIG. 2.If the length of the H-shaped region is not sufficiently exaggerated toaccount for this pullback, the active areas defined by the legs of theH-shaped regions will disappear under the polysilicon 44, and it willnot be possible to contact them with the local interconnect 48. On theother hand, exaggerating the size of the H-shaped regions results in alarger size for each static random access memory cell.

[0040] The layout shown in FIGS. 5-7 reduces this encroachment problem,and thus reduces the need to exaggerate the lengths of the legs of theH-shaped active areas, by interconnecting the ends of the active areas.Thus, instead of spaced apart H-shaped active areas, active areas in thegeneral shape of a stepladder are formed (FIG. 7). Each ladder-shapedactive area has two spaced apart parallel sides, and a plurality ofparallel spaced apart areas (“rungs”) extending transversely between theparallel sides. This results in space saving, so that smaller staticrandom access memory cells are produced.

[0041] Note, however, that the purpose of separating the H-shaped activeareas in the first place was to provide electrical isolation betweenactive area regions (e.g., to provide electrical isolation between thedrains 70 and 72 of the p-channel transistors P1 and P2). The twop-channel transistors P1 and P2 share a common active area in theembodiment of FIGS. 5-7. More particularly, the drains 70 and 72 of thep-channel transistors P1 and P2 share a common active area in theembodiment of FIGS. 5-7.

[0042] The inventor of the present invention has accomplished thenecessary isolation by providing an isolator which isolates the pulluptransistor P1 from the pullup transistor P2. More particularly, theisolator comprises an isolation gate 84 defined relative to the commonactive area, between the drains 70 and 72 of the p-channel transistorsP1 and P2. In the illustrated embodiment, polysilicon is employed todefine the isolation gate 84. By causing polysilicon 44 to intersect thecommon active area, an isolation p-channel transistor 82 is defined(FIG. 5) between the gates 70 and 72.

[0043] The isolation gate is adapted to be connected to a voltage higherthan Vss. More particularly, the isolation gate is adapted to beconnected to a voltage sufficient to turn off (tri-state) the isolationtransistor, and thus isolate gate 70 from gate 72 (except for leakagecurrent). In one embodiment, the isolation gate 84 is connected to thesources of the p-channel transistors P1 and P2. More particularly, inthe illustrated embodiment, the isolation gate 84 is connected to theVcc metal.

[0044] Other than the common active area shared by drains 70 and 72, andthe isolation gate 84, the embodiment shown in FIGS. 5-7 issubstantially identical to the embodiment shown in FIGS. 2-3, likereference numerals indicating like components. The silicon processingsteps employed in forming the embodiment shown in FIG. 6 is substantialidentical to the silicon processing steps employed in manufacturing theembodiment shown in FIG. 2, except for the formation of the commonactive area (the ladder shaped active areas of FIG. 7 are formed at thesame stage in the process, and in a similar manner, as the H-shapedactive areas of FIG. 2). FIG. 5 also shows a parasitic transistor 40formed because of an intersection of polysilicon with an active area,which is not shown in FIG. 1.

[0045] Thus, a layout for manufacturing static random access memorycells has been provided which results in reduced size of each cell. Eachcell includes first and second cross-coupled invertors, each invertorincluding a first p-channel pullup transistor, and a first n-channelpulldown transistor in series with the first p-channel pulluptransistor; the first and second pullup transistors sharing a commonactive area; and an isolator isolating the first pullup transistor fromthe second pullup transistor.

[0046] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A static random access memory cell comprising: a first p-channelpullup transistor having a gate, drain, and source; a first n-channelpulldown transistor having a gate, drain, and source; a second p-channelpullup transistor having a gate, drain, and source; a second n-channelpulldown transistor having a gate, drain, and source; the source of thefirst pullup transistor being adapted to be connected to a firstvoltage; the source of the second pullup transistor being adapted to beconnected to the first voltage; the drain of the first pulldowntransistor being connected to the drain of the first pullup transistor;the drain of the second pulldown transistor being connected to the drainof the second pullup transistor; the source of the first pulldowntransistor being adapted to be connected to a second voltage lower thanthe first voltage; the source of the second pulldown transistor beingadapted to be connected to the second voltage; the gate of the firstpullup transistor being connected to the gate of the first pulldowntransistor; the gate of the second pullup transistor being connected tothe gate of the second pulldown transistor; the first pullup transistorand the first pulldown transistor together defining a first invertorhaving an output defined by the drain of the first pulldown transistorand an input defined by the gate of the first pulldown transistor, thesecond pullup transistor and the second pulldown transistor togetherdefining a second invertor having an output defined by the drain of thesecond pulldown transistor and an input defined by the gate of thesecond pulldown transistor, the input of the first invertor beingconnected to the output of the second inverter, and the input of thesecond invertor being connected to the output of the first invertor; anda p-channel isolation transistor connected between the drain of thefirst pullup transistor and the drain of the second pullup transistor,and having a gate.
 2. A static random access memory cell in accordancewith claim 1 wherein the source of the first p-channel transistor isconnected to the source of the second p-channel transistor, and to thegate of the p-channel isolation transistor.
 3. A static random accessmemory cell in accordance with claim 1 wherein the p-channel isolationtransistor comprises an active area that is common to both the firstpullup transistor and the second pullup transistor.
 4. A static randomaccess memory cell in accordance with claim 1 wherein the source of thefirst pullup transistor is connected to the first voltage, wherein thesource of the second pullup transistor is connected to the firstvoltage, wherein the source of the first pulldown transistor isconnected to the second voltage, wherein the gate of the p-channelisolation transistor is connected to the first voltage, and wherein thesource of the second pulldown transistor is connected to the secondvoltage.
 5. A static random access memory cell in accordance with claim1 wherein the p-channel isolation transistor comprises an active areathat is common to both the drain of the first pullup transistor and thedrain of the second pullup transistor.
 6. A static random access memorycell in accordance with claim 1 and further comprising a first bit line;a second bit line; a word line; a first access transistor having a firstactive terminal connected to the output of the first invertor, having asecond active terminal connected to the first bit line, and having agate adapted to be connected to the word line; and a second accesstransistor having a first active terminal connected to the output of thesecond invertor, having a second active terminal connected to the secondbit line, and having a gate connected to the word line.
 7. A staticrandom access memory cell comprising: a first invertor including a firstp-channel pullup transistor, and a first n-channel pulldown transistorin series with the first p-channel pullup transistor; a second invertorincluding a second p-channel pullup transistor, and a second n-channelpulldown transistor in series with the second n-channel pulluptransistor, the first invertor being cross-coupled with the secondinvertor, the first and second pullup transistors sharing a commonactive area; a first access transistor having an active terminalconnected to the first invertor; a second access transistor having anactive terminal connected to the second invertor; and an isolatorisolating the first pullup transistor from the second pullup transistor.8. A static random access memory cell in accordance with claim 7 whereinthe first and second pullup transistors have respective gates, whereinthe common active area is shared by the gates of the first and secondpullup transistors, and wherein the isolator isolates the gate of thefirst pullup transistor from the gate of the second pullup transistor.9. A static random access memory cell in accordance with claim 7 whereinthe isolator comprises an isolation gate adapted to be biased to isolatethe first pullup transistor from the second pullup transistor.
 10. Astatic random access memory cell in accordance with claim 9 wherein theisolation gate cooperates with the active area to define a p-channeltransistor.
 11. A static random access memory cell in accordance withclaim 10 wherein the gate of the isolator is connected to a voltageeffective to tri-state the transistor.
 12. A static random access memorycell in accordance with claim 9 wherein the isolation gate cooperateswith the active area to define a p-channel transistor, the gate of theisolator being connected to a positive voltage.
 13. A static randomaccess memory cell in accordance with claim 8 wherein the first invertorhas an output, and the active terminal of the first access transistor isconnected to the output of the first invertor; and wherein the secondinvertor has an output, and the active terminal of the second accesstransistor is connected to the output of the second invertor.
 14. Amethod of manufacturing a static random access memory cell includingfirst and second cross-coupled invertors, each invertor including ap-channel transistor connected in series with an n-channel transistor,the p-channel transistors having sources that are connected to eachother and that are adapted to be connected to a common first voltage,and the p-channel transistors having respective drains; the n-channeltransistors having respective sources that are connected to each otherand that are adapted to be connected to a common second voltage, lowerthan the first voltage, and the n-channel transistors having respectivedrains; the method comprising the following steps: providing a siliconsubstrate; defining the first and second invertors relative to thesubstrate such that the first and second invertors include an activearea common to drains of the p-channel transistors; and defining anisolation gate relative to the common active area, between the drains ofthe p-channel transistors.
 15. A method of manufacturing a static randomaccess memory cell in accordance with claim 14 wherein the step ofdefining the isolation gate comprises using polysilicon to define thegate.
 16. A method of manufacturing a static random access memory cellin accordance with claim 14 and further comprising the step ofconnecting the sources of the p-channel transistors to the firstvoltage, connecting the sources of the nchannel transistors to thesecond voltage, and connecting the isolation gate to a voltage higherthan the second voltage.
 17. A method of manufacturing a static randomaccess memory cell in accordance with claim 14 and further comprisingthe step of connecting the isolation gate to the first voltage.
 18. Amethod of manufacturing a static random access memory cell in accordancewith claim 14 wherein the step of defining the isolation gate comprisesforming polysilicon on the common active area.
 19. A method ofmanufacturing a static random access memory cell in accordance withclaim 14 wherein the first invertor has an output, and wherein thesecond invertor has an output, and further comprising the step ofdefining a first access transistor having a first active terminalconnected to the output of the first invertor, having a second activeterminal adapted to be connected to a first bit line, and having a gateadapted to be connected to a word line; and defining a second accesstransistor having a first active terminal connected to the output of thesecond invertor, having a second active terminal adapted to be connectedto a second bit line, and having a gate adapted to be connected to theword line.
 20. A method of manufacturing a wafer including a pluralityof static random access memory cells, each cell including first andsecond cross-coupled invertors, each invertor including a pchanneltransistor connected in series with an nchannel transistor, thep-channel transistors having sources that are connected together andthat are adapted to be connected to a common first voltage, and havingrespective drains; the n-channel transistors having sources that areconnected together and that are adapted to be connected to a commonsecond voltage, lower than the first voltage, and having respectivedrains; the method comprising the following steps: providing a siliconsubstrate; defining active areas relative to the substrate for thestatic random access memory cells, the active areas including an activearea having the general shape of a stepladder, including two parallel,spaced apart sides, and a plurality of parallel, spaced apart portionsextending between the sides, such that the sides define drains of aplurality of the p-channel transistors; and defining respectiveisolation gates relative to active areas, between the drains of thep-channel transistors within each static random access memory cell. 21.A method of manufacturing a wafer in accordance with claim 20 whereinthe step of defining the isolation gates comprises using polysilicon todefine the gates.
 22. A method of manufacturing a wafer in accordancewith claim 20 and further comprising the step of connecting the sourcesof the p-channel transistors to the first voltage and connecting thesources of the n-channel transistors to the second voltage.
 23. A methodof manufacturing a wafer in accordance with claim 22 and furthercomprising the step of connecting the isolation gates to a voltagehigher than the second voltage.
 24. A method of manufacturing a wafer inaccordance with claim 22 and further comprising the step of connectingthe isolation gates to the first voltage.
 25. A method of manufacturinga wafer in accordance with claim 22 wherein the step of defining theisolation gates comprises forming polysilicon on the active area betweenthe drains of the p-channel transistors of each static random accessmemory cell.
 26. A method of manufacturing a wafer in accordance withclaim 22 wherein, for each static random access memory cell, the firstinvertor has an output, and the second invertor has an output, themethod comprising the step of defining a first access transistor, foreach static random access memory cell, having a first active terminalconnected to the output of the first invertor of that cell, having asecond active terminal adapted to be connected to a bit line, and havinga gate adapted to be connected to a word line; and defining a secondaccess transistor, for each static random access memory cell, having afirst active terminal connected to the output of the second invertor ofthat cell, having a second active terminal adapted to be connected to abit line different from the first mentioned bit line, and having a gateadapted to be connected to the word line.